1. Field of the Invention
The present invention generally relates to the field of testing integrated circuit chips, and more specifically, to testing memory logic on an integrated circuit.
2. Description of the Related Art
Embedded memories require the utilization of built-in self-test (“BIST”) to evaluate whether they are good, i.e., operational, and to perform needed redundancy calculations. Conventional BIST systems have typically been separated into a controller and a collar (or wrapper). In convention integrated circuit chip designs the collar is close to the memory, while the controller is remote from the collar and shared by a number of collars. In these conventional designs, the idea is to place dedicated resources in the collars and place shared logic in the controller.
A problem with conventional BIST system approaches is that dedicated high-speed interface lines are required between the controller and each collar. Because the controller is geographically remote from the collars, circuit timing becomes a challenge. Unfortunately, these challenges translate to increased design cycle times and increased design complexities to ensure circuit timing needs are met.
Another problem with a conventional BIST system has to do with memories that reside in different clock domains. When memories reside in different clock domains, a conventional BIST system requires a minimum of one controller per clock domain. Due to the high-speed interface as described above, the physical proximity of the controller to collared memories must be taken into account. Specifically, systems are required to have more than one controller required per clock domain. In turn, this causes additional challenges for planning the insertion of a conventional BIST because it must consider the clock domains for the memory to be tested as well as the physical locations of the memory within the layout of the device. Both result in increased design cycle time and expense.
Yet another problem with conventional BIST systems is limited information available to the tester with respect to integrated circuit chip operational failures. Conventional BIST systems do diagnose failures, when present, within a chip. However, such systems are unable to provide information on what specifically failed within the integrated circuit chip.
Therefore, in view of the above, there is a need for a system and process to test memory logic in an integrated circuit chip design that includes scheduling and diagnostics for memory logic testing and provides information on failure specifications.